Vertical memory devices and methods of manufacturing the same

ABSTRACT

A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a first direction that is vertical to a top surface of the substrate, a plurality of gate lines stacked on top of each other on the substrate, a plurality of wiring over the gate lines and electrically connected to the gate lines, and an identification pattern on the substrate at the same level as a level of at least one of the rings. The gate lines surround the channels. The gate lines are spaced apart from each other along the first direction.

CROSS-REFERENCE TO RELATED APPLICATION APPLICATIONS

This application is a reissue application for U.S. Pat. No. 10,304,847,issued on May 28, 2019 on U.S. Ser. No. 15/923,408, filed on Mar. 16,2018, which is a divisional of Ser. U.S. Non-Provisional Application No.15/612,229 (now U.S. Pat. No. 10,090,314), filed on Jun. 2, 2017, whichis a divisional of U.S. Non-Provisional application Ser. No. 15/179,068(now U.S. Pat. No. 9,698,151), filed on Jun. 10, 2016, which claimspriority under 35 U.S.C. § 119 to U.S. Provisional Application No.62/238,918, filed on Oct. 8, 2015, in the USPTO, and Korean PatentApplication No. 10-2015-0166489, filed on Nov. 26, 2015, in the KoreanIntellectual Property Office (KIPO). The entire contents of each of theabove-referenced applications are incorporated by reference herein.

BACKGROUND

1. Field

Example embodiments relate to vertical memory devices and methods ofmanufacturing the same. More particularly, example embodiments relate tovertical memory devices including vertically stacked gate lines andmethods of manufacturing the same.

2. Description of Related Art

Recently, a vertical memory device including a plurality of memory cellsstacked vertically with respect to a surface of a substrate has beendeveloped for achieving a high degree of integration. In the verticalmemory device, a channel having a pillar shape or a cylindrical shapemay protrude vertically from the surface of the substrate, and gatelines surrounding the channel may be repeatedly stacked.

As the degree of integration of the vertical memory device becomesgreater, the number of the gate lines, and the number of blocksincluding the channel and the gate lines may increase. Thus, acomplexity of the vertical memory device may be intensified.

SUMMARY

Example embodiments provide a vertical memory device having improvedprocess and operation reliability.

Example embodiments provide a method of manufacturing a vertical memorydevice having improved process and operation reliability.

According to example embodiments, a vertical memory device includes asubstrate; a plurality of channels on the substrate, the channelsextending in a first direction that is vertical to a top surface of thesubstrate; a plurality of gate lines stacked on top of each other on thesubstrate, the gate lines surrounding the channels, the gate linesspaced apart from each other along the first direction; a plurality ofwirings over the gate lines and electrically connected to the gatelines; and an identification pattern on the substrate at the same levelas a level of at least one of the wirings.

In example embodiments, the gate lines at each level may include a stepportion extending in a second direction parallel to the top surface ofthe substrate, and the wirings may be electrically connected to the stepportions of corresponding gate lines.

In example embodiments, the identification pattern may be spaced apartfront the channels in the second direction with respect to the wirings.

In example embodiments, the vertical memory device may further include adummy wiring on the substrate between the identification pattern and oneof the wirings.

In example embodiments, the vertical memory device may further include abit line extending in a third direction that may be parallel to the topsurface of the substrate and crosses the second direction. The bit linemay be connected to at least one of the channels. The identificationpattern and the bit line may be at the same level.

In example embodiments, the identification pattern may be between thebit line and the wirings in a plan view.

In example embodiments, the wirings may be disposed at a plurality oflevels over the substrate, and the identification pattern may be at thesame level as a level of a lowermost wiring of the wirings.

In example embodiments, the wirings may be disposed at a plurality oflevels over the substrate, and the identification pattern may bedisposed at the same level as that of an uppermost wiring of thewirings.

In example embodiments, the wirings may be disposed at a plurality oflevels over the substrate, and the identification pattern, may bedisposed at two or more levels of the plurality of the levels.

In example embodiments, the identification pattern may include one of aplurality of dot patterns, a plurality of line patterns, or acombination of a dot pattern and a line pattern.

In example embodiments, the identification pattern may include theplurality of the line patterns, and the line patterns may cross eachother.

In example embodiments, the identification pattern and the wiring mayinclude a conductive material that is the same.

According to example embodiments, a vertical memory device includes asubstrate; a plurality of cell blocks on the substrate; a plurality ofwirings; and an identification pattern on the substrate. Each of thecell blocks includes: a plurality of channels extending in a firstdirection vertical to a top surface of the substrate, and a plurality ofgate lines stacked on top of each other on the substrate. The gate linessurround the channels. The gate lines are spaced apart from each otheralong the first direction. The plurality of wirings are over the gatelines and electrically connected to the gate lines. The identificationpattern corresponds to at least one of the plurality of the cell blocks.

In example embodiments, the identification pattern may be disposed atthe same level as a level of at least one of the wirings.

In example embodiments, the gate lines may extend in a second directionparallel to the top surface of the substrate. The plurality of the cellblocks may be spaced apart from each other along a third direction thatmay be parallel to the top surface of the substrate. The third directionmay cross the second direction.

In example embodiments, the vertical memory device may farther include acutting pattern on the substrate between the cell blocks.

In example embodiments, the substrate may include a cell region and anextension region. The channels may be on the cell region. The endportions of the gate lines may be on the extension region. The cuttingpattern may extend over the cell region and the extension region.

In example embodiments, the cutting pattern may be a common source line.

In example embodiments, the vertical memory device may further include aplurality of block groups on the substrate and arranged in the thirddirection. Each of the block groups may include a group of the cellblocks.

In example embodiments, the identification pattern may be provided pereach block group.

In example embodiments, at least one of the cell blocks may furtherinclude dummy wirings adjacent to the wirings.

In example embodiments, a dummy wiring included in a cell block of thecell blocks in which the identification pattern may be provided may havea different shape from those of remaining dummy wirings of the dummywirings.

According to example embodiments, a vertical memory device includes asubstrate including a cell region, an extension region and a peripheralregion; a plurality of vertical channels on the cell region; gate lineson the substrate, the gate lines surrounding the vertical channels, thegate lines stacked on top of each other on a top surface of thesubstrate, the gate lines extending over the cell region and theextension region; contacts electrically connected to the gate lines onthe extension region; wirings electrically connected to the gate linesvia the contacts, the wirings extending from the extension region to theperipheral region; and an identification pattern on the substrate overan uppermost gate line of the gate lines.

In example embodiments, the identification pattern may be at the samelevel as that of at least one of the wirings.

In example embodiments, the vertical channels may extend in a firstdirection that may be vertical to a top surface of the substrate, andthe gate lines may extend in a second direction and a third directionthat may be parallel to the top surface of the substrate and may crosseach other.

In example embodiments, the extension region may include a firstextension region and a second extension region. The first extensionregion may be adjacent to both lateral portions of the cell region inthe second direction. The second extension region may be adjacent toboth lateral portions of the cell region in the third direction. Theperipheral region may include a first peripheral region and a secondperipheral region. The first peripheral region may be adjacent to alateral portion of the first extension region in the second direction.The second peripheral region may be adjacent to a lateral portion of thesecond extension region in the third direction.

In example embodiments, the contacts and the wirings may be arranged onthe first extension region, and the second extension region may serve asa dummy region. The first peripheral region may be a decoder region, andthe second peripheral region may be a page buffer region.

In example embodiments, the vertical memory device may include aplurality of identification patterns on the substrate. Theidentification patterns may include the identification pattern. Theidentification patterns may be on at least two of the cell region, thefirst extension region, the second extension region, the firstperipheral region, and the second peripheral region.

In example embodiments, the gate lines may include a ground selectionline (GSL), word lines and a string selection line (SSL) sequentiallystacked from the top surface of the substrate. The first extensionregion may include a first contact region and a second contact regionfacing each other with respect to the cell region.

In example embodiments, the wirings may include a first wiringelectrically connected to the GSL and the word lines on the firstcontact region, and a second wiring electrically connected to the SSL onthe second contact region.

In example embodiments, the identification pattern may include a firstidentification pattern adjacent to the first wiring, and a secondidentification pattern adjacent to the second wiring.

According to example embodiments, a method of manufacturing a verticalmemory device includes forming a mold structure on a substrate, theforming a mold structure including forming insulating interlayers andsacrificial layers alternately and repeatedly on the substrate; formingchannels that extend through the mold structure on the substrate;forming an opening that linearly extends through the mold structure;removing the sacrificial layers through the opening; forming gate linesin spaces from which the sacrificial layers are removed; forming firstwirings electrically connected to the gate lines; forming anidentification pattern on the substrate at the same level as a level ofthe first wirings; detecting a failure by applying an electrical signalthrough the first wirings; and forming a second wiring over the firstwirings, the second wiring being electrically connected to at least oneof the first wirings.

In example embodiments, the detecting the failure may include using theidentification pattern as one of an address identification guide and areference pattern.

In example embodiments, the method may include forming a plurality ofcell blocks on the substrate. The cell blocks may be defined by thechannels, the gate lines and the first wirings. The detecting thefailure may include using the identification pattern as the addressidentification guide or the reference pattern for selecting a desiredcell block from the plurality of the cell blocks.

In example embodiments, the first wirings and the identification patternmay be formed by the same patterning process.

According to example embodiments, a vertical memory device includes asubstrate including a cell region, extension region, and a peripheralregion; a cell block including gate lines stacked on top of each other,and channels extending vertically through the gate lines; an insulationlayer on the cell block, the insulation layer extending over the cellregion, the extension region, and the peripheral region; and aconductive pattern on the insulation layer. The conductive patternincludes wirings and an identification pattern that are spaced aparteach other on the insulation layer. The wirings are electricallyconnected to the gate lines, and the identification pattern is at thesame level above the substrate as a level of the wirings.

In example embodiments, the conductive pattern may include bit lines atthe same level above the substrate as the wirings and the identificationpattern, the bit lines may be electrically connected to the channels,and the bit lines may be spaced apart from the wirings and theidentification pattern.

In example embodiments, the conductive pattern may include a dummypattern, the dummy pattern may be spaced apart from the wirings and theidentification pattern at the same level, and the identification patternmay be over the peripheral region.

In example embodiments, the vertical memory device may further includebit lines on the cell block and a second insulation layer on top of thebit lines and the insulation layer. The insulation layer may be a firstinsulation layer, and the conductive pattern may be on top of the secondinsulation layer.

In example embodiments, the wirings and the identification pattern maybe formed of the same material.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other features of inventive concepts will be apparentfrom the more particular description of non-limiting embodiments ofinventive concepts, as illustrated in the accompanying drawings in whichlike reference characters refer to like parts throughout the differentviews. The drawings are not necessarily to scale, emphasis instead beingplaced upon illustrating principles of inventive concepts. In thedrawings:

FIG. 1 is a schematic top plan view illustrating regions of a verticalmemory device in accordance with example embodiments;

FIGS. 2 to 4 are a top plan view and cross-sectional views illustratinga vertical memory device in accordance with example embodiments;

FIG. 5 is a schematic view illustrating an arrangement of wiringsincluded in cell blocks;

FIGS. 6 to 9 illustrate shapes of identification patterns in accordancewith example embodiments;

FIGS. 10 to 35 are cross-sectional views and top plan views illustratinga method of manufacturing a vertical memory device in accordance withexample embodiments;

FIGS. 36 to 38 are cross-sectional views illustrating vertical memorydevices in accordance with example embodiments;

FIG. 39 is a schematic top plan view illustrating regions of a verticalmemory device in accordance with example embodiments;

FIGS. 40 to 42 are a top plan view and cross-sectional viewsillustrating vertical memory devices in accordance with exampleembodiments;

FIG. 43 is a schematic top plan view illustrating regions of a verticalmemory device in accordance with example embodiments; and

FIG. 44 is a top plan view illustrating a vertical memory device inaccordance with example embodiments.

DESCRIPTION OF EXAMPLE EMBODIMENTS

Various example embodiments will be described more fully hereinafterwith reference to the accompanying drawings, in which exampleembodiments are shown. Inventive concept mays, however, be embodied inmany different forms and should not be construed as limited to theexample embodiments set forth herein. Rather, these example embodimentsare provided so that this description will be thorough and complete, andwill fully convey the scope of inventive concepts to those skilled inthe art. In the drawings, the sizes and relative sizes of layers andregions may be exaggerated for clarity. Like reference characters and/ornumerals in the drawings denote like elements, and thus theirdescription may not be repeated.

It will be understood that when an element or layer is referred to asbeing “on,” “connected to” or “coupled to” another element or layer, itcan be directly on, connected or coupled to the other element or layeror intervening elements or layers may be present. In contrast, when anelement is referred to as being “directly on,” “directly connected to”or “directly coupled to” another element or layer, there are nointervening elements or layers present. Other words used to describe therelationship between elements or layers should be interpreted in a likefashion (e.g., “between” versus “directly between,” “adjacent” versus“directly adjacent,” “on” versus “directly on”). As used herein, theterm “and/or” includes any and all combinations of one or more of theassociated listed items.

It will be understood that, although the terms first, second, third,fourth etc. may be used herein to describe various elements, components,regions, layers and/or sections, these elements, components, regions,layers and/or sections should not be limited by these terms. These termsare only used to distinguish one element, component, region, layer orsection from another region, layer or section. Thus, a first element,component, region, layer or section discussed below could be termed asecond element, component, region, layer or section without departingfrom the teachings of inventive concepts.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper” and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the exemplary term “below” can encompass both anorientation of above and below. The device may be otherwise oriented(rotated 90 degrees or at other orientations) and the spatially relativedescriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particularexample embodiments only and is not intended to be limiting of inventiveconcepts. As used herein, the singular forms “a,” “an” and “the” areintended to include the plural forms as well, unless the context clearlyindicates otherwise. It will be further understood that the terms“comprises” and/or “comprising,” when used in this specification,specify the presence of stated features, integers, steps, operations,elements, and/or components, but do not preclude the presence oraddition of one or more other features, integers, steps, operations,elements, components, and/or groups thereof.

Example embodiments are described herein with reference tocross-sectional illustrations that are schematic illustrations ofidealized example embodiments (and intermediate structures). As such,variations from the shapes of the illustrations as a result, forexample, of manufacturing techniques and/or tolerances, are to beexpected. Thus, example embodiments should not be construed as limitedto the particular shapes of regions illustrated herein but are toinclude deviations in shapes that result, for example, frommanufacturing. For example, an implanted region illustrated as arectangle will, typically, have rounded or curved features and/or agradient of implant concentration at its edges rather than a binarychange from implanted to non-implanted region. Likewise, a buried regionformed by implantation may result in some implantation in the regionbetween the buried region and the surface through winch the implantationtakes place. Thus, the regions illustrated in the figures are schematicin nature and their shapes are not intended to illustrate the actualshape of a region of a device and are not intended to limit the scope ofinventive concepts.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this inventive concept belongs. Itwill be further understood that terms, such as those defined in commonlyused dictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art andwill not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein.

Although corresponding plan views and/or perspective views of somecross-sectional view(s) may not be shown, the cross-sectional view(s) ofdevice structures illustrated herein provide support for a plurality ofdevice structures that extend along two different directions as would beillustrated in a plan view, and/or in three different directions aswould be illustrated in a perspective view. The two different directionsmay or may not be orthogonal to each other. The three differentdirections may include a third direction that may be orthogonal to thetwo different directions. The plurality of device structures may beintegrated in a same electronic device. For example, when a devicestructure (e.g., a memory cell structure or a transistor structure) isillustrated in a cross-sectional view, an electronic device may includea plurality of the device structures (e.g., memory cell structures ortransistor structures), as would be illustrated by a plan view of theelectronic device. The plurality of device structures may be arranged inan array and/or in a two-dimensional pattern.

A direction substantially vertical to a top surface of a substrate isreferred to as a first direction, and two directions substantiallyparallel to the top surface of the substrate and crossing each other arereferred to as a second direction and a third direction. For example,the second direction and the third direction are substantiallyperpendicular to each other. Additionally, a direction indicated by anarrow and a reverse direction thereof are considered as the samedirection. The above mentioned definitions of the directions are thesame throughout all the figures in this specification.

FIG. 1 is a schematic top plan view illustrating regions of a verticalmemory device in accordance with example embodiments. FIGS. 2 to 4 are atop plan view and cross-sectional views illustrating a vertical memorydevice in accordance with example embodiments. For convenience ofdescriptions, an illustration of some insulating structures is omittedin FIG. 2.

Referring to FIGS. 1 and 2, the vertical memory device may include asubstrate 100 including a cell region C, extension regions E1 and E2,and peripheral regions P1 and P2.

As illustrated in FIG, 2, pads 137 disposed on vertical channelstructures 136 (see FIGS. 3 and 4) may be arranged on the cell region C,and a plurality of gate lines 160 (e.g., 160a through 160f) may surroundthe vertical channel structures 136 and may be stacked along the firstdirection.

The extension regions may include a first extension region E1 and asecond extension region E2. For example, a pair of the first extensionregions E1 may be located at both lateral portions of the cell region Cin the second direction. A first peripheral region P1 may be adjacent tothe first extension region E1 at a peripheral portion of the substrate100 in the second direction.

In example embodiments, step portions of the gate lines 160 may bearranged on the first extension region E1. A first wiring 180 may beelectrically connected to each step portion via a first contact 172. Thestep portion of the gate line 160 on the first extension region E1 mayserve as a contact pad.

For example, the first wiring 180 may extend in the second directionfrom the first extension region E1 to the first peripheral region P1.

A wiring pad 181 may be formed at an end portion of the first wiring 180on the first peripheral region P1. For example, the first wiring 180 maybe electrically connected to a peripheral circuit contact 176 (see FIG.3) via the wiring pad 181.

Dummy wirings 184 may be further arranged on the first peripheralcircuit region P1 to be adjacent to the first wirings 180. In exampleembodiments, the dummy wirings 184 may be at the same level as that ofthe first wirings 180, and may be utilized as a mark for identifying thefirst peripheral region P1.

A pair of the second extension regions E2 may be located at both lateralportions of the cell region C in the third direction. The step portionsof the gate lines 160 may be also arranged on the second extensionregion E2. In example embodiments, the first wirings 180 and/or thefirst contacts 172 may not be arranged on the second extension regionE2, and the second extension region E2 may be allotted as a dummyregion.

A second peripheral region P2 may be adjacent to the second extensionregion E2 at a peripheral portion of the substrate 100 in the thirddirection.

A cutting pattern 157 may be disposed on the cell region C and the firstextension region E1, and may extend through the gate lines 160.

In example embodiments, the cutting pattern 157 may extend in the secondregion throughout the cell region C and the first extension region E1,and may intersect or cut the gate lines 160 along the first direction. Aplurality of the cutting patterns 157 may be arranged along the thirddirection on the cell region C.

A plurality of cell blocks may be defined by the cutting pattern 157. Asillustrated in FIG. 1, first to third cell blocks CB1, CB2 and CB3 maybe defined by two cutting patterns 157. The number of the cuttingpatterns 157, and the number of the cell blocks may be greater dependingon a capacity and a degree of integration of the vertical memory device.

Each cell block may include the gate lines 160 that may be cut by thecutting pattern 157 and stacked along the first direction, the verticalchannel structures 136 extending through the gate lines 160, and thefirst wirings 180 electrically connected to the step portions of thegate lines 160. In example embodiments, the cell block may furtherinclude the dummy wirings 184.

The first peripheral region P1 may serve as a decoder region forselecting the cell block or applying a signal to the first wirings 180.

In example embodiments, an identification pattern 186 may be included inat least one of the cell blocks. In example embodiments, theidentification pattern 186 may be at the same level as that of the firstwirings 180, and may be disposed on the first peripheral region P1.

In example embodiments, the identification pattern 186 may be adjacentto the dummy wiring 184. For example, as illustrated in FIG. 1, theidentification pattern 186 may be included in the second cell block CB2(or next to the second cell block CB2 in the second direction). In thiscase, the dummy wiring 184 included in the second cell block CB2 mayhave a different shape from those of the dummy wirings 184 in the firstand third cell blocks CB1 and CB3.

For example, the dummy wiring 184 included in the second cell block CB2may be shorter than those included in the first and third cell blocksCB1 and CB3.

The identification pattern 186 may be utilized as an addressidentification guide for, e.g., applying a signal and/or selecting thecell block on the first peripheral region P1. A desired cell block maynot be easily determined when searching an address or performing variousdetections because the cell blocks may have a structure substantiallythe same as or similar to each other and may include repeated patterns.However, the identification pattern 186 may be included at least one ofthe cell blocks, and a reference pattern may be provided for the addressidentification.

Further, the dummy wirings 184 may be also utilized as the referencepattern for identifying addresses and/or the regions of the verticalmemory device.

For example, as illustrated in FIGS. 1 and 2, the identification pattern186 may include a combination of line patterns that may extend indifferent directions. However, a shape of the identification pattern 186may be modified in consideration of the convenience of identification ora patterning process.

A bit line 182 may extend in, e.g., the third direction and may beelectrically connected to the vertical channel structures 136 via thepads 137. A plurality of the bit lines 182 may be arranged along thesecond direction on the cell region C.

In example embodiments, the bit line 182 may extend throughout the cellregion C and the pair of the second extension regions E2 adjacent to thecell region C. In example embodiments, the bit line 182 may extend tothe second peripheral region P2. The second peripheral region P2 mayserve as a page buffer region.

Hereinafter, elements and constructions of the vertical memory devicewill be described in more detail with reference to FIGS. 3 and 4. FIGS.3 and 4 are cross-sectional views taken along lines I-I′ and II-II′ ofFIG. 2, respectively.

The substrate 100 may include a semiconductor material, e.g., siliconand/or germanium. In example embodiments, the substrate 100 may includesingle crystalline silicon. For example, the substrate 100 may serve asa body and/or a p-type well of the vertical memory device.

The vertical channel structure 136 may extend through the gate lines 160and insulating interlayer patterns 116 (e.g., 116a through 116g) in thefirst direction on the cell region C. The vertical channel structure 136may include a channel 132, a dielectric layer structure 130 and afilling insulation pattern 134. In example embodiments, a semiconductorpattern 127 may be interposed between the substrate 100 and the verticalchannel structure 136.

The channel 132 may have a hollow cylindrical shape or a cup shape. Thechannel 132 may include polysilicon or single crystalline silicon, andmay include p-type impurities such as boron (B) in a portion thereof.

The filling insulation pattern 134 may fill an inner space of thechannel 132, and may have a solid cylindrical shape or a pillar shape.The filling insulation pattern 134 may include an insulation materialsuch as silicon oxide. In example embodiments, the channel 132 may havea pillar shape or a solid cylindrical shape, and the filling insulationpattern 134 may be omitted.

The dielectric layer structure 130 may be formed on an outer sidewall ofthe channel 132. The dielectric layer structure 130 may have a strawshape or a cylindrical shell shape.

The dielectric layer structure 130 may include a tunnel insulationlayer, a charge storage layer and a blocking layer which may besequentially stacked from the outer sidewall of the channel 132. Theblocking layer may include silicon oxide or a metal oxide such ashafnium oxide or aluminum oxide. The charge storage layer may include anitride such as silicon nitride or a metal oxide, and the tunnelinsulation layer may include an oxide such as silicon oxide. Forexample, the dielectric layer structure 130 may have anoxide-nitride-oxide (ONO) layered structure.

The semiconductor pattern 127 may include single crystalline silicon orpolysilicon. The semiconductor pattern 127 may be in contact withbottoms of the dielectric layer structure 130 and the charnel 132.

The pad 137 may be formed on the vertical channel structure 136. Forexample, the pad 137 may be electrically connected to, e.g., the bitline 182, and may serve as a source/drain region through which chargesmay be moved or transferred to the channel 132. The pad 137 may includepolysilicon or single crystalline silicon, and may be optionally dopedwith n-type impurities such as phosphorus (P) or arsenic (As).

As illustrated in FIG. 2, a plurality of the pads 137 may be arrangedalong the second direction on the cell region C such that a pad row maybe defined, and a plurality of the pad rows may be arranged in the thirddirection. The vertical channel structures 136 may be also arrangedaccording to an arrangement of the pads 137. For example, a plurality ofthe vertical channel structures 136 may be arranged along the seconddirection on the cell region C to form a channel row, and a plurality ofthe channel rows may be arranged in the third direction.

The gate lines 160 may be formed on an outer sidewall of the dielectriclayer structure 130 or the semiconductor pattern 127, and may be spacedapart from each other along the first direction. In example embodiments,each gate line 160 may partially surround the channels 132 or thevertical channel structures 136 included in at least one of the channelrows and may extend in the second direction.

In example embodiments, each gate line 160 may surround the number ofthe channel rows, e.g., 4 channel rows. In this case, a gate line stackstructure may be defined by the 4 channel rows and the gate lines 160surrounding the 4 channel rows. A plurality of the gate line stackstructures may be arranged along the third direction.

In example embodiments, widths or length of the gate lines 160 in thesecond direction may be reduced along the first direction from the topsurface of the substrate 100. For example, as illustrated in FIG. 3, aplurality of the gate lines 160 may be stacked in a pyramidal shape or astepped shape.

Accordingly, the gate line 160 of each level may include a step portionprotruding in the second direction from the gate line 160 at an upperlevel thereof, and the step portions of the gate lines 160 may bearranged on the first extension region E1.

The gate lines 160 may include a ground selection line (GSL), a wordline and a string selection line (SSL). For example, a lowermost gateline 160a may serve as the GSL. An uppermost gate line 169f may serve asthe SSL. The gate lines 160b to 160e between the GSL and the SSL mayserve as the word lines.

The GSL (e.g., the gate line 160a) may laterally surround thesemiconductor pattern 127. The word lines (e.g., the gate lines 160b to160e) and the SSL (e.g., the gate line 160f) may laterally surround thechannel 132 or the dielectric layer structure 130.

The gate lines may be formed at increased levels in consideration of acircuit design and a degree of integration of the vertical memorydevice, e.g. 16 levels, 24 levels, 32 levels, 48 levels, etc. The SSLsmay be formed at two or more levels.

The gate line 160 may include a metal such as tungsten (W), a metalnitride and/or a metal silicide. In example embodiments, the gate line160 may have a multi-layered structure including a metal nitride such astungsten nitride, and a metal.

Insulating interlayer patterns 116 may be disposed between the gatelines 160 neighboring in the first direction. The insulating interlayerpattern 116 may include a silicon oxide-based material, e.g., silicondioxide (SiO₂), silicon oxycarbide (SiOC) or silicon oxyfluoride (SiOF).The gate lines 160 included in one gate line stack structure may beinsulated from each other by the insulating interlayer patterns 116. Inexample embodiments, the insulating interlayer patterns 116 may bestacked along the first direction in a pyramidal shape or a steppedshape substantially the same as or similar to that of the gate lines160.

A peripheral circuit including, e.g., a transistor may be formed on thefirst peripheral region P1 of the substrate 100. The transistor mayinclude a gate structure 108 and a first impurity region 103. The gatestructure 108 may include a gate insulation pattern 102, a gateelectrode 104 and a gate mask 106. In example embodiments, a peripheralcircuit protection layer 109 may be formed on the first peripheralregion P1.

A mold protection layer 120 covering stepped portions of the gate lines160 may be formed on a lateral portion of the gate line stack structure.The mold protection layer 120 may also cover the peripheral circuitprotection layer 109 on the first peripheral region P1.

The peripheral circuit protection layer 109 and the mold protectionlayer 120 may include an insulation material, e.g., silicon oxide.

A first upper insulation layer 140 may be formed on the mold protectionlayer 120, an uppermost insulating interlayer pattern 116g and the pads137.

The cutting pattern 157 may be interposed between the gate line stackstructures. An insulation pattern 155 may be formed on a sidewall thecutting pattern 157. For example, the cutting pattern 157 and theinsulation pattern 155 may extend through the first upper insulationlayer 140, the gate lines 160, the insulating interlayer patterns 116and the mold protection layer 120, and may extend in the seconddirection. The gate line stack structure including the number of thechannel rows (e.g., 4 channel rows) may be defined by the cuttingpattern 157 and the insulation pattern 155.

In example embodiments, the cutting pattern 157 may serve as a commonsource line (CSL) of the vertical memory device. The cutting pattern 157and the gate lines 160 included in the gate line stack structure may beinsulated from each other by the insulation pattern 155.

The cutting pattern 157 may include a metal, e.g., tungsten or copper.The insulation pattern 155 may include, e.g., silicon oxide.

An impurity region 105 (see FIG. 4) may be formed at an upper portion ofthe substrate 100 under the cutting pattern 157 and the insulationpattern 155. The first impurity region 105 may extend in the seconddirection together with the cutting pattern 157.

A second upper insulation layer 170 may be formed on the first upperinsulation layer 140, and may cover the cutting pattern 157 and theinsulation pattern 155.

The first contact 172 may extend through the second upper insulationlayer 170, the first upper insulation layer 140, the mold protectionlayer 120 and/or the insulating interlayer pattern 116 to beelectrically connected to the gate line 160 at each level.

In example embodiments, the first contacts 172 may be distributed on thefirst extension region E1, and may be electrically connected to the stepportions of the gate lines 160. In example embodiments, the firstcontact 172 may be provided per each step portion of the gate lines 160included in one gate line stack structure.

A bit line contact 174 electrically connected to the pad 137 may bedisposed on the cell region C. For example, the bit line contact 174 maybe formed through the second upper insulation layer 170 and the firstupper insulation layer 140 to be in contact with the pad 137. Aplurality of the bit line contacts 174 may be formed in an arrangementsubstantially the same as or similar to that of the pads 137.

In example embodiments, the peripheral circuit contact 176 may be formedon the first peripheral circuit region P1. The peripheral circuitcontact 176 may extend through, e.g., the second upper insulation layer170, the first upper insulation layer 140, the mold protection layer 120and the peripheral circuit protection layer 109, and may be electricallyconnected to the first impurity region 103.

The first wiring 180 may be disposed on the second upper insulationlayer 170 to be electrically connected to the first contact 172. Inexample embodiments, the first wirings 180 may be provided based on thenumber of the gate lines 160 included in one of the gate lines stackstructure. For example, six first wirings 180 may correspond to the oneof the gate line stack structure.

In example embodiments, the first wiring 180 may extend in the seconddirection throughout the first extension region E1 and the firstperipheral region P1, and may be also electrically connected to theperipheral circuit contact 176 via the wiring pad 181 (see FIG. 2).

The bit line 182, the dummy wiring 184 and the identification pattern186 may be disposed on the second upper insulation layer 170 asdescribed with reference to FIG. 2. In example embodiments, the bit line182, the first wiring 180, the dummy wiring 184 and the identificationpattern 186 may be located at substantially the same level.

FIG. 5 is a schematic view illustrating an arrangement of wiringsincluded in cell blocks.

As described with reference to FIGS. 1 to 4, the first wirings 180 andthe dummy wirings 184 may be included in each cell block, and aplurality of the cell blocks may be repeatedly arranged along the thirddirection. Thus, wirings may be repeatedly arranged along the thirddirection in substantially the same or similar patterns.

Referring to FIG. 5, for example, first to third cell blocks CB1, CB2and CB3 may define one block group BG, and a plurality of the blockgroups BG may be arranged along the third direction.

In example embodiments, at least one identification pattern 186 may beprovided in each block group BG. For example, the identification pattern186 may be provided in the first cell block CB1 of each block group BG.

As described above, the wirings arranged in the repeated patterns may bedivided based on the cell block and the block group BG, and theidentification pattern 186 may be inserted in each block group. Thus, anaddress identification may be easily conducted when applying a signal,detecting defects, etc., and a desired cell block may be selectedprecisely.

The number of the cell blocks included in the block group BG, and alocation and a shape of the identification pattern 186 may not belimited as illustrated in FIG. 5.

FIGS. 6 to 9 illustrate shapes of identification patterns in accordancewith example embodiments.

Referring to FIG. 6, an identification pattern 286a may include acombination of a plurality of dot patterns or island patterns. Thus, theidentification pattern 286a may be easily differentiated front theadjacent wirings having a linear shape.

Referring to FIG. 7, an identification pattern 286b may include acombination of line patterns extending in the same direction. The linepattern included in the identification pattern 286b may be shorter thanthe adjacent wiring (e.g., the first wiring 180 and the dummy wiring184). Thus, the identification pattern 286b may be easily differentiatedfrom the adjacent wirings.

Referring to FIG. 8, an identification pattern 286c may include linepatterns extending in different direction. For example, theidentification pattern 286c may include line patterns crossing eachother.

Referring to FIG. 9, an identification pattern 286d may include acombination of a plurality of dot patterns or island patterns and atleast one line pattern.

However, the shape of the identification pattern may be properlymodified in consideration of distinctiveness relative to the adjacentwirings. In example embodiments, the identification pattern may have acharacter (or letter) shape, e.g., one of alphabet characters or Koreancharacters. In example embodiments, the identification pattern may havea shape conferring an order, e.g., a number or a Roman alphabet.

FIGS. 10 to 35 are cross-sectional views and top plan viewsillustrating, a method of manufacturing a vertical memory device inaccordance with example embodiments. For example, FIGS. 10 to 35illustrate a method of manufacturing the vertical memory deviceillustrated is FIGS. 1 to 4.

Specifically, FIGS. 13, 20, 24, 27, 31 and 33 are top plan viewsillustrating the method. FIGS. 10, 11, 12, 14, 16, 18, 22, 25, 29, 32and 34 are cross-sectional views taken along a line I-I′ designated inthe top plan views and along the first direction. FIGS. 15, 17, 19, 21,23, 26, 28, 30 and 35 are cross-sectional views taken along a lineII-II′ designated in the top plan views and along the first direction.

For convenience of descriptions, an illustration of some insulatingstructures is omitted in FIGS. 13, 20, 24, 27, 31 and 33.

Referring to FIG. 10, a peripheral circuit may be formed on a substrate100.

As described with reference to FIG. 1, the substrate 100 may include acell region C, first and second extension regions E1 and E2, and firstand second peripheral regions P1 and P2. In example embodiments, theperipheral circuit may be formed on the first peripheral region P1adjacent to the first extension region E1.

The substrate 100 may include a semiconductor (e.g., single crystallinesilicon or single crystalline germanium) and may serve as a body and/ora p-type well of the vertical memory device. The peripheral circuit mayinclude, e.g., a transistor defined by a gate structure 108 and a firstimpurity region 103.

For example, a gate insulation layer, a gate electrode layer and a gatemask layer may be sequentially formed on the substrate 100. The gatemask layer may be partially etched to form a gate mask 106. The gateelectrode layer and the gate insulation layer may be partially etchedusing the gate mask 106 as an etching mask to form a gate electrode 104and a gate insulation pattern 102. Accordingly, the gate structure 108including, the gate insulation pattern 102, the gate electrode 104 andthe gate mask 106 sequentially stacked on the substrate 100 may beformed.

The gate insulation layer may be formed of silicon oxide or a metaloxide. The gate electrode layer may be formed of a metal, a metalnitride, a metal silicide or doped polysilicon. The gate mask layer maybe formed of silicon nitride. The gate insulation layer, the gateelectrode layer and the gate mask layer may be formed by at least one ofa chemical vapor deposition (CVD) process, a plasma enhanced chemicalvapor deposition (PECVD) process, a high density plasma chemical vapordeposition (HDP-CVD) process, an atomic layer deposition (ALD) processor a sputtering process. In example embodiments, the gate insulationlayer may be formed by performing a thermal oxidation process on a topsurface of the substrate 100.

An ion-implantation process may be performed using the gate structure108 as an implantation mask to form the first impurity region 103 at anupper portion of the substrate 100 in the first peripheral region P1adjacent to the gate structure 108.

In example embodiments, a spacer including, e.g., silicon nitride may befurther formed on a sidewall of the gate structure 108.

A peripheral circuit protection layer 109 covering the transistor may befurther formed. For example, a protection layer covering the firstimpurity region 103 and the gate structure 108 may be formed on thesubstrate 100. A portion of the protection layer formed on the cellregion C and the first extension region E1 may be removed to form theperipheral circuit protection layer 109. The protection layer may beformed as an oxide layer.

Referring to FIG. 11, a stepped mold structure may be formed on the cellregion C and the extension regions E1 and E2 of the substrate 100.

In example embodiments, insulating interlayers 112 (e.g., 112a through112g) and sacrificial layers 114 (e.g., 114a through 114f) may be formedon the substrate 100 to form a mold structure.

The insulating interlayer 112 may be formed of an oxide-based material,e.g., silicon dioxide, silicon oxycarbide and/or silicon oxyfluoride.The sacrificial layer 114 may be formed of a material that may have anetching selectivity with respect to the insulating interlayer 112 andmay be easily removed by a wet etching process. For example, thesacrificial layer 114 may be formed of a nitride-based material, e.g.,silicon nitride and/or silicon boronitride.

The insulating interlayer 112 and the sacrificial layer 114 may beformed by a CVD process, a PECVD process, a spin coating process, etc.In example embodiments, a lowermost insulating interlayer 112a may beformed by a thermal oxidation process or a radical oxidation process ona top surface of the substrate 100. In example embodiments, an uppermostinsulating interlayer 112g may be formed to have a relatively largethickness in consideration of a formation of a pad 137 (see FIG. 18).

The sacrificial layers 114 may be removed in a subsequent process toprovide spaces for a GSL, a word line and an SSL. Thus, the number ofthe insulating interlayers 112 and the sacrificial layers 114 may bedetermined in consideration of the number of the GSL, the word line andthe SSL. FIG. 11 illustrates that the sacrificial layers 114 and theinsulating interlayers 112 are formed at 6 levels and 7 levels,respectively. However, the number of the insulating interlayers 112 andthe sacrificial layers 114 may increase or decrease depending on adesired degree of integration of the vertical memory device.

Subsequently, a lateral portion of the mold structure may be partiallyetched in, e.g., a stepwise manner to form the stepped mold structure.

For example, a photoresist pattern (not illustrated) covering the cellregion C and the extension regions E1 and E2 may be formed on theuppermost insulating interlayer 112g. Peripheral portions of theuppermost insulating interlayer 112g and an uppermost sacrificial layer114f may be removed using the photoresist pattern as an etching mask. Aperipheral portion of the photoresist pattern may be partially removedso that a width of the photoresist pattern may be reduced. Peripheralportions of insulating interlayers 112g and 112f, and sacrificial layers114f and 114e may be etched using the photoresist pattern again as anetching mask. Etching processes may be repeated with a desired (and/oralternatively predetermined) etching amount in a similar manner asdescribed above to obtain the stepped mold structure illustrated in FIG.11, and the peripheral regions P1 and P2 and the peripheral circuitprotection layer 109 may be exposed again.

Referring to FIG. 12, a mold protection layer 120 covering a lateralportion of the stepped mold structure may be formed on the substrate 100and the peripheral circuit protection layer 109.

For example, an insulation layer covering the stepped mold structure andthe peripheral circuit protection layer 109 may be formed on thesubstrate 100 using, e.g., silicon oxide by a CVD process or a spincoating process. An upper portion of the insulation layer may beplanarized until the uppermost insulating interlayer 112g is exposed toform the mold protection layer 120. The planarization process mayinclude a chemical mechanical polish (CMP) process and/or an etch-backprocess.

In example embodiments, the mold protection layer 120 may be formed of amaterial substantially the same as or similar to that of the insulatinginterlayer 112. In this case, the mold protection layer 120 may beintegral or merged with the insulating interlayer 112.

Referring to FIGS. 13 to 15, channel holes 125 may be formed through thestepped mold structure on the cell region C.

For example, a hard mask (not illustrated) may be formed on theuppermost insulating interlayer 112g and the mold protection layer 120.The insulating interlayers 112 and the sacrificial layers 114 of thestepped mold structure may be partially etched by performing, e.g., adry etching process. The hard mask may be used as an etching mask toform the channel hole 125. The channel hole 125 may extend in the firstdirection from the top surface of the substrate 100, and the top surfaceof the substrate 100 may be partially exposed by the channel hole 125.The hard mask may be formed of silicon-based or carbon-based spin-onhardmask (SOH) materials, and/or a photoresist material. The hard maskmay be removed by an ashing process and/or a strip process after theformation of the channel holes 125.

As illustrated in FIGS. 13, 14, and 15, a plurality of the channel holes125 may be formed in the second direction to form a channel hole row. Aplurality of the channel hole rows may be formed in the third direction.The channel hole rows may be arranged such that the channel holes 125may be formed in a zigzag arrangement along the second direction and/orthe third direction.

In example embodiments, a semiconductor pattern 127 may be formed at alower portion of the channel hole 125. For example, the semiconductorpattern 127 may be formed by a selective epitaxial growth (SEG) processusing the top surface of the substrate 100 exposed through the channelhole 125 as a seed. In example embodiments, a top surface of thesemiconductor pattern 127 may be positioned between a top surface of afirst sacrificial layer 114a and a bottom surface of a secondsacrificial layer 114b.

Referring to FIGS. 16 and 17, a vertical channel structure 136 fillingthe channel hole 125 may be formed on the semiconductor pattern 127.

In example embodiments, a dielectric layer may be formed along sidewallsof the channel holes 125, and top surfaces of the uppermost insulatinginterlayer 112g, the semiconductor pattern 127 and the mold protectionlayer 120. Upper and lower portions of the dielectric layer may beremoved by an etch-back process to form a dielectric layer structure 130on the sidewall of the channel hole 125.

A channel layer and a filling insulation layer filling remainingportions of the channel holes 125 may be sequentially formed along thetop surfaces of the uppermost insulating interlayer 112g and the moldprotection layer 120, an inner wall of the dielectric layer structure130, and the top surface of the semiconductor pattern 127. Upperportions of the channel layer and the filling insulation layer may beplanarized by, e.g., a CMP process until the uppermost insulatinginterlayer 112g and/or the mold protection layer 120 may be exposed.Accordingly, the vertical channel structure 136 including the dielectriclayer structure 130, a channel 132 and a filling insulation pattern 134may be formed in each channel hole 125.

The dielectric layer may be formed by sequentially forming a blockinglayer, a charge storage layer and a tunnel insulation layer. In exampleembodiments, the dielectric layer may be formed as anoxide-nitride-oxide (ONO) layered structure. The blocking layer, thecharge storage layer and the tunnel insulation layer may be formed by aCVD process, a PECVD process, an ALD process, etc.

The channel layer may be formed of polysilicon or amorphous siliconwhich is optionally doped with impurities. In example embodiments, aheat treatment or a laser beam irradiation may be further performed onthe channel layer. In this case, the channel layer may be transformed toinclude single crystalline silicon. The filling insulation layer may beformed using, e.g., silicon oxide or silicon nitride. The channel layerand the filling insulation layer may be formed by a CVD process, a PECVDprocess, an ALD process, a PVD process, a sputtering process, etc.

The dielectric layer structure 130 may have a straw shape or acylindrical shell shape surrounding an outer sidewall of the channel132. The channel 132 may have a substantially cup shape. The fillinginsulation pattern 134 may have a pillar shape inserted in the channel132.

Referring to FIGS. 18 and 19, the pad 137 capping an upper portion ofthe channel hole 125 may be formed.

For example, an upper portion of the vertical channel structure 136 maybe partially removed by, e.g., an etch-back process to form a recess. Apad layer may be formed on the dielectric layer structure 130, thechannel 132, the filling insulation pattern 134, the uppermostinsulating interlayer 112g and the mold protection layer 120 tosufficiently fill the recess. An upper portion of the pad layer may beplanarized by, e.g., a CMP process until top surfaces of the uppermostinsulating interlayer 112g and/or the mold protection layer 120 may beexposed to form the pad 137 from a remaining portion of the pad layer.

For example, the pad layer may be formed using polysilicon optionallydoped with n-type impurities by a sputtering process or an ALD process.In example embodiments, a preliminary pad layer including amorphoussilicon may be formed, and then a crystallization process may beperformed thereon to form the pad layer.

According to the arrangement of the channel row, a plurality of the pads137 may define a pad row in the uppermost insulating interlayer 112g,and a plurality of the pad rows may be formed along the third direction.A channel row may be defined under the pad row, and a plurality of thechannel rows may be arranged along the third direction.

A first upper insulation layer 140 may be formed on the uppermostinsulating interlayer 112g, the pads 137 and the mold protection layer120. The first upper insulation layer 140 may be formed of silicon oxideby a CVD process, a spin coating process, etc.

Referring to FIGS. 20 and 21, an opening 150 extending through thestepped mold structure may be formed.

For example, a hard mask (not illustrated) covering the pads 137 andpartially exposing the first upper insulation layer 140 between some ofthe channel rows may be formed. The first upper insulation layer 140,the mold protection layer 120, the insulating interlayers 112 and thesacrificial layers 114 may be partially etched by, e.g., a dry etchingprocess using the hard mask as an etching mask to form the opening 150.The hard mask may be formed using a photoresist material or an SOHmaterial. The hard mask may be removed by an ashing process and/or astrip process after the formation of the opening 150.

For example, the opening, 150 may extend in the second direction, and aplurality of the openings 150 may be formed along the third direction.The number of the channel rows may be arranged between the openings 150neighboring in the third direction. For example, as illustrated in FIG.20, four channel rows may be included between the neighboring openings150. However, the number of the channel rows between the openings 105may be properly adjusted in consideration of a circuit design or adegree of integration of the vertical memory device.

As illustrated in FIG. 21, after the formation of the opening 150, theinsulating interlayers 112 and the sacrificial layers 114 may be changedinto insulating interlayer patterns 116 (e.g., 116a through 116g) andsacrificial patterns 118 (e.g., 118a through 118f). The insulatinginterlayer pattern 116 and the sacrificial pattern 118 at each level mayhave a plate shape extending in the second direction.

In example embodiments, the top surface of the substrate 100, andsidewalls of the insulating interlayer patterns 116 and the sacrificialpatterns 118 may be exposed through the opening 150.

Referring to FIGS. 22 and 23, the sacrificial patterns 118 exposed bythe opening 150 may be removed. In example embodiments, the sacrificialpatterns 118 may be removed by a wet etching process using, e.g.,phosphoric acid as an etchant solution.

A gap 152 may be defined by a space from which the sacrificial pattern118 is removed. A sidewall of the vertical channel structure 136 may bepartially exposed by the gap 152. In example embodiments, a sidewall ofthe semiconductor pattern 127 may be exposed by a lowermost gap 152.

As illustrated in FIG. 22, the gap 152 may extend in the seconddirection at each level, and may be blocked by the mold protection layer120.

Referring to FIGS. 24 to 26, gate lines 160 (e.g., 160a through 160f)may be formed in the gaps 152. Accordingly, the sacrificial layer 114and the sacrificial pattern 118 of each level may be replaced with thegate line 160.

In example embodiments, a gate electrode layer may be formed on theexposed outer sidewalls of the vertical channel structures 136, surfacesof the insulating interlayer patterns 116, the top surface of thesubstrate 100 exposed through the opening 150, and a top surface of thefirst upper insulation layer 140. The gate electrode layer maysufficiently fill the gaps 152 and at least partially fill the opening150.

The gate electrode layer may be formed using a metal or a metal nitride.For example, the gate electrode layer may be formed of tungsten,tungsten nitride, titanium, titanium nitride, tantalum, tantalumnitride, platinum, etc. In example embodiments, the gate electrode layermay be formed as a multi-layered structure including a barrier layerformed of a metal nitride, and a metal layer. The gate electrode layermay be formed by a CVD process, a PECVD process, an ALD process, a PVDprocess, a sputtering process, etc.

In example embodiments, an interface layer (not illustrated) may beformed along inner walls of the gaps 152 and the surfaces of theinsulating interlayer patterns 116 prior to the formation of the gateelectrode layer. The interlace layer may be formed of silicon oxide or ametal oxide.

Subsequently, the gate electrode layer may be partially removed to formthe gate line 160 in the gap 152 at each level.

For example, an upper portion of the gate electrode layer may beplanarized by a CMP process until the first upper insulation layer 140may be exposed. Portions of the gate electrode layer formed in theopening 150 and on the top surface of the substrate 100 may be etched toobtain the gate lines 160.

The gate lines 160 may include the GSL (e.g., the gate line 160a), theword line (e.g., the gate lines 160b through 160e) and the SSL (e.g.,the gate line 160f) sequentially stacked and spaced apart from oneanother in the first direction. The number of the levels at which theGSL, the word line and the SSL are formed may increase in considerationof a circuit design and a capacity of the vertical memory device.

The gate line 160 at each level may have a shape substantially the sameas or similar to that of the sacrificial pattern 118. The gate line 160at each level may include a step portion protruding in the seconddirection from an upper gate line 160 thereof.

Referring to FIGS. 27 and 28, an ion-implantation process may beperformed to form a second impurity region 105 at an upper portion ofthe substrate 100 exposed through the opening 150. The second impurityregion 105 may extend in, e.g., the second direction.

Subsequently, an insulation pattern 155 and a cutting pattern 157filling the opening 150 may be formed on the second impurity region 105.

For example, an insulation layer including silicon oxide may be formedalong the top surface of the first upper insulation layer 140, and asidewall and a bottom of the opening 150. Upper and lower portions ofthe insulation layer may be removed by an etch-back process to form theinsulation pattern 150 on the sidewall of the opening 150. A conductivelayer filling a remaining portion of the opening 150 may be formed onthe first upper insulation layer 140. An upper portion of the conductivelayer may be planarized by a CMP process to form the cutting pattern157. The conductive layer may be formed of a metal, a metal silicideand/or doped polysilicon by a sputtering process or an ALD process.

In example embodiments, the cutting pattern 157 and the insulationpattern 155 may extend in the second direction together in the opening150. In example embodiments, the cutting pattern 157 may serve as a CSLof the vertical memory device, and may be insulated from the gate lines160 by the insulation pattern 155.

A gate line stack structure including the gate lines 160, the insulatinginterlayer patterns 116, and the channel rows extending through the gatelines 160 and the insulating interlayer patterns 116 may be defined bythe cutting patterns 157 neighboring in the third direction.

Referring to FIGS. 29 and 30, a second upper insulation layer 170covering the cutting pattern 157 may be formed on the first upperinsulation layer 140.

For example, the second upper insulation layer 170 may be formed of asilicon oxide-based material substantially the same as or similar tothat of the first upper insulation layer 140 by a CVD process, a spincoating process, etc.

Referring to FIGS. 31 and 32, contacts may be formed through the secondand first upper insulation layers 170 and 140.

In example embodiments, first contacts 172 (e.g., 172a through 172f) maybe formed on the first extension region E1 to be landed on the stepportions of the corresponding gate lines 160 (e.g., 160a through 160f).

In example embodiments, the first contacts 172a to 172e which may beconnected to the GSL and the word lines may be formed through the secondupper insulation layer 170, the first upper insulation layer 140, themold protection layer 120 and the insulating interlayer patterns 116b to116f.

In example embodiments, the first contact 172f which may be connected tothe SSL may be formed through the second upper insulation layer 170, thefirst upper insulation layer 140 and the uppermost insulating interlayerpattern 116g.

In example embodiments, a bit line contact 174 may be formed on the cellregion C. The bit line contact 174 may be formed through the secondupper insulation layer 170 and the first upper insulation layer 140 tobe electrically connected to the pad 137. In example embodiments, aperipheral circuit contact 176 may be further formed on the firstperipheral region P1. The peripheral circuit contact 176 may be formedthrough the second upper insulation layer 170, the first upperinsulation layer 140, the mold protection layer 120 and the peripheralcircuit protection layer 109, and may be electrically connected to thefirst impurity region 103.

In example embodiments, contact holes for forming the bit line contact174, the first contacts 172 and the peripheral circuit contact 176 maybe concurrently formed by the substantially the same photo-lithographyprocess. A first conductive layer filling the contact holes may beformed, and an upper portion of the first conductive layer may beplanarized by a CMP process until a top surface of the second upperinsulation layer 170 may be exposed. Accordingly, the bit line contact174, the first contacts 172 and the peripheral circuit contact 176 maybe substantially simultaneously formed from the first conductive layer.

In example embodiments, the photo-lithography process for forming thebit line contact 174, the first contacts 172 and the peripheral circuitcontact 176 may be divided into a plurality of photo-lithographyprocesses.

Referring to FIGS. 33 to 35, wirings electrically connected to thecontacts may be formed on the second upper insulation layer 170.Additionally, an identification pattern 186 may be formed together withthe wirings.

First wirings 180 (e.g., 180a through 180f) may be patterned to beelectrically connected to the respective contacts 172 (e.g., 172athrough 172f) which may be connected to the gate line stack structure.The first wirings 180 may extend in the second direction from the firstextension region E 1 to a portion of the first peripheral region P1. Inexample embodiments, dummy wirings 184 may be formed on the firstperipheral region P1 together with the first wirings 180. The dummywirings 184 may include a plurality of line patterns, and may be formedper each gate line stack structure or each cell block.

The bit line 182 may extend in the third direction on the cell region C,and may be patterned to be electrically connected to a plurality of thebit line contacts 174.

In example embodiments, the identification pattern 186 may be formed atone or more of the gate line stack structures and the cell blocks. Theidentification pattern 186 may be formed to be adjacent to the dummywirings 184 on the first peripheral region P1. The identificationpattern 186 may be formed in various shapes to be distinguished from thedummy wirings 184 and/or the first wirings 180 as described withreference to FIGS. 6 to 9.

In example embodiments, the first wiring 180, the dummy wiring 184 andthe identification pattern 186 may be formed concurrently bysubstantially the same etching process with respect to a secondconductive layer. In example embodiments, the bit line 182 may be alsoformed from the second conductive layer.

The first and second conductive layers may be formed of a metal, e.g.,copper, aluminum, etc., by a sputtering process or an ALD process.

In example embodiments, for example, an operational failure test of thecell blocks may be conducted using the identification pattern 186 as anaddress identification guide. If the cell blocks are determined asnormal through the operational failure test, an additional wiringsbuild-up may be performed on the first wirings 180.

FIGS. 36 to 38 are cross-sectional views illustrating vertical memorydevices in accordance with example embodiments. FIGS. 36 to 38 arepartial cross-sectional views illustrating an upper portion of thevertical memory device which includes a wiring structure.

Detailed descriptions on elements and constructions substantially thesame as or similar to those illustrated with reference to FIGS. 1 to 5are omitted herein.

Referring to FIG. 36, the wiring structure may include a first contact172, a first bit line contact 174a, a peripheral circuit contact 176, afirst bit line 182a, a first wiring 180 and a first dummy wiring 184a.The first bit line 182a, the first wiring 180 and the first dummy wiring184a may be formed at the substantially same level (e.g., on the secondupper insulation layer 170).

In example embodiments, additional wirings may be disposed over thefirst bit line 182a, the first wiring 180 and the first dummy wiring184a. For example, a third upper insulation layer 200 covering the firstbit line 182a, the first wiring 180 and the first dummy wiring 184a maybe formed on the second upper insulation layer 170.

A second bit line contact 204 and a second contact 202 may be formedthrough the third insulation layer 200 to be electrically connected tothe first bit line 182a and the first wiring 180, respectively.

A second wiring 210, a second bit line 212 and a second dummy wiring 214may be formed on the third upper insulation layer 200. The second wiring210 may be electrically connected to the first wiring 180 via the secondcontact 202. The second bit line 212 may be electrically connected tothe first bit line 182a via the second bit line contact 204. The secondwiring 210 may extend throughout the first extension region E1 and thefirst peripheral region P1. The second bit line 213 may extend on thecell region C in, e.g., the third direction.

The second dummy wiring 214 may be provided per each cell block, and maybe spaced apart from the second wiring 210 to be disposed on the firstperipheral region P1.

In example embodiments, an identification pattern 216 may be disposed ona portion of the third upper insulation layer 200 of the firstperipheral region P1 to be adjacent to the second dummy wiring 214.

In example embodiments, the second wiring 210, the second bit line 212,the second dummy wiring 214 and the identification pattern 216 may beformed from substantially the same patterning process with respect to,e.g., a third conductive layer.

Referring to FIG. 37, additional wirings may be further disposed overthe second bit line 212, the second wiring 210 and the second dummywiring 214.

For example, a fourth upper insulation layer 220 covering the second bitline 212, the second wiring 210 and the second dummy wiring 214 may beformed on the third upper insulation layer 200.

A third contact 222 may be formed through the fourth upper insulationlayer 220 to be electrically connected to the second wiring 210.

In example embodiments, a third wiring 230 and a third dummy wiring 234may be formed on the fourth upper insulation layer 220. The third wiring230 may be electrically connected to the second wiring 210 via the thirdcontact 222. The third wiring 230 may extend throughout the firstextension region E1 and the first peripheral region P1. The third dummywiring 234 may be provided per each cell block, and may be spaced apartfrom the third wiring 230 to be disposed on the first peripheral regionP1.

In example embodiments, an identification pattern 236 may be disposed ona portion of the fourth upper insulation layer 220 of the firstperipheral region P1 to be adjacent to the third dummy wiring 234.

In example embodiments, the third wiring 230, the third dummy wiring 234and the identification pattern 236 may be formed from substantially thesame patterning process with respect to, e.g., a fourth conductivelayer.

As illustrated in FIGS. 3, 36 and 37, the identification pattern may bedisposed at a wiring level corresponding to the first wiring 180, thesecond wiring 210 or the third wiring 230 to be provided as an addressidentification guide.

In example embodiments, the identification pattern may be disposed attwo or more of the wiring levels corresponding to the first wiring 180,the second wiring 210 or the third wiring 230.

Referring to FIG. 38, for example, a first identification pattern 186amay be disposed at the same wiring level as that of the first wiring180, and a second identification pattern 236a may be disposed at thesame wiring level as that of the third wiring 230.

In example embodiments, the first identification pattern 186a may serveas an address identification guide for a failure test. The secondidentification pattern 236a may serve as an address identification guidefor applying a driving signal.

FIG. 39 is a schematic top plan view illustrating regions of a verticalmemory device in accordance with example embodiments. FIGS. 40 to 42 area top plan view and cross-sectional views illustrating vertical memorydevices in accordance with example embodiments. Specifically, FIG. 40 isa top plan view of the vertical memory device. FIGS. 41 and 42 arecross-sectional views taken along a line I-I′ indicated in FIG. 40.

Detailed descriptions on elements and/ or constructions substantiallythe same as or similar to those described with reference to FIGS. 1 to4, and/or FIGS. 36 to 38 are omitted herein.

Referring to FIGS. 39 and 40, as also illustrated with reference toFIGS. 1 and 2, the vertical memory device or the substrate 100 mayinclude the cell region C, the first and second extension regions E1 andE2, and the first and second peripheral regions P1 and P2.

A plurality of the cell blocks CB1, CB2 and CB3 may be defined by thecutting pattern 157 extending throughout the cell region C and the firstextension region E1. Step portions of the gate lines 160 included ineach cell block may be arranged on the first extension region E1.

In example embodiments, an identification pattern 187 may be disposed onan end portion of the cell region C adjacent to the first extensionregion E1. For example, the identification pattern 187 may be disposedon a remaining space of the cell region C between a region in which thevertical channel structures 136 may be formed and a region in which anuppermost first contact 172f may be formed.

In example embodiments, the identification pattern may be disposed at aboundary between the cell region C and the first extension region E1.

As described above, the identification pattern 187 may be moved from thefirst peripheral region P1 to the end portion or the boundary of thecell region C so that an area of the first peripheral region P1 may besaved or reduced.

Referring to FIG. 41, the identification pattern 187 may be disposed atsubstantially the same level as that of the first wiring 180. Forexample, the identification pattern 187 may be disposed on the secondupper insulation layer 170 to be adjacent to the bit line 182.

Referring to FIG. 42, as also described with reference to FIG. 36,additional wirings may be further formed over the first bit line 174a,the first wiring 180 and the first dummy wiring 184a. For example, thesecond bit line 212, the second wiring 210 and the second dummy wiring214 may be disposed on the third upper insulation layer 200.

In example embodiments, all identification pattern 216 may be disposedat substantially the same level as that of the second wiring 210. Forexample, the identification pattern 216 may be disposed on the thirdupper insulation layer 200 to be adjacent to the second bit line 212.

FIG. 43 is a schematic top plan view illustrating regions of a verticalmemory device in accordance with example embodiments.

Referring to FIG. 43, as also illustrated with reference to FIGS. 1 and2, the vertical memory device may include the cell region C, the firstand second extension regions E1 and E2, and the first and secondperipheral regions P1 and P2. The cell blocks CB1, CB2 and CB3 may bedefined by a cutting pattern on the cell region C and the firstextension region E1.

In example embodiments, the second extension region E2 may be allottedas a dummy region, and the second peripheral region P2 may serve as apage buffer region.

In example embodiments, an identification pattern may be disposed on thesecond extension region E2 and/or the second peripheral region P2.

In example embodiments, the identification pattern may include a firstidentification pattern 188a disposed on the second extension region E2,and a second identification pattern 188b disposed on the secondperipheral region P2.

The identification pattern may be provided on the peripheral regionand/or the extension region in the third direction. Thus, an addressidentification guide may be also provided when, e.g., applying a signalthrough a bit line.

FIG. 44 is a top plan view illustrating a vertical memory device inaccordance with example embodiments. Detailed descriptions on elementsand/or constructions substantially the same as or similar to thoseillustrated with reference to FIGS. 1 and 2 are omitted herein.

Referring to FIG. 44, as also described with reference to FIG. 1, thefirst extension region and the first peripheral region P1 may bearranged sequentially from the cell region C. The first extensionregions and the first peripheral regions P1 may be substantiallysymmetrical with respect to the cell region C.

In example embodiments, the first extension region may include a firstcontact region EC1 and a second contact region EC2. The first contactregion EC1 and the second contact region EC2 may be adjacent to bothlateral portions of the cell region C in the second direction.

The gate lines 160 (e.g., 160a through 160g) may be stacked along thefirst direction on the cell region C and the first extension region.

In example embodiments, a cell block or a gate line stack structure ofthe vertical memory device may include SSLs of at least two levels. Forexample, a lowermost gate line 160a may serve as a GSL, and twouppermost gate lines 160f and 160g may serve as the SSL. Gate lines 160bto 160e between the GSL and the SSL may serve as word lines.

The first contacts 172 and the first wirings 180 electrically connectedto the GSL and the word lines may be disposed on the first contactregion EC1. In example embodiments, the first contact 172 and the firstwiring 180 electrically connected to a lower SSL 160f may be alsodisposed on the first contact region EC1.

The dummy wirings 184 may be disposed on the first peripheral region P1adjacent to the first contact region EC1.

A second contact 240 and a second wiring 245 electrically connected tothe SSL may be disposed on the second contact region EC2. In exampleembodiments, the second contact 240 and the second wiring 245 may beelectrically connected to an upper SSL 160g.

The first wiring 180 and the second wiring 245 may extend in the seconddirection, and may be disposed at substantially the same wiring level.In example embodiments, the second wiring 245 may be disposed at anupper wiring level of the first wiring 180.

A plurality of cell blocks including, e.g., first to third cell blocksCB1, CB2 and CB3 may be defined by the cutting pattern intersecting thecell region C and the first extension region.

In example embodiments, an identification pattern may be disposed at thewiring level. The identification pattern may include a plurality ofpatterns having different shapes or being limited at different regions.

For example, a first identification pattern 189a may be disposed on thefirst peripheral region P1 adjacent to the first contact region EC1, andmay serve as an identification pattern for the second cell block CB2.

A second identification pattern 189b may have a different shape fromthat of the first identification pattern 189a. For example, the secondidentification pattern 1896 may be disposed on the first peripheralregion P1 adjacent to the second contact region EC2. The secondidentification pattern 189b may serve as an identification pattern forthe first cell block CB1, and may serve as an address identificationguide for selecting the cell block through the SSL.

A third identification pattern 189c may have a different shape from thatof the first identification pattern 189a. For example, the thirdidentification pattern 189c may be disposed on an end portion of thecell region C adjacent to the second contact region EC2. The thirdidentification pattern 189c may serve as an identification pattern forthe third cell block CB3, and may serve as an address identificationguide for selecting the cell block through the SSL.

The first to third identification patterns 189a, 189b and 189c may bedisposed at the same wiring level or different wiring levels.

As described above, the identification patterns may be arranged indifferent shapes and/or in different regions. Thus, addressidentification guides for selecting the cell block, applying a signalthrough, e.g., the first wiring 180, detecting failures of the cellblock, etc., may be concurrently provided.

According to example embodiments of the present inventive concepts, anidentification pattern for searching an address of a cell block may beformed. The identification pattern may be formed by the same patterningprocess as that for forming wirings over the gate line stack structure.The identification pattern and the wirings may be located at the samelevel. The identification pattern may be formed over the gate line stackstructure, and thus may be easily identified without an additionaloptical device. Thus, the identification pattern may serve as areference when detecting a failed cell block and identifying a cellblock for applying a signal.

In example embodiments, a nonvolatile memory may be embodied to includea three dimensional (3D) memory array. The 3D memory array may bemonolithically formed on a substrate (e.g., semiconductor substrate suchas silicon, or semiconductor-on-insulator substrate). The 3D memoryarray may include two or more physical levels of memory cells having anactive area disposed above the substrate and circuitry associated withthe operation of those memory cells, whether such associated circuitryis above or within such substrate. The layers of each level of the arraymay be directly deposited on the layers of each underlying level of thearray.

In example embodiments, the 3D memory array may include vertical NANDstrings that are vertically oriented such that at least one memory cellis located over another memory cell. The at least one memory cell maycomprise a charge trap layer.

The following patent documents, which are hereby incorporated byreference in their entirety, describe suitable configurations forthree-dimensional memory arrays, in which the three-dimensional memoryarray is configured as a plurality of levels, with word lines and/or bitlines shared between levels: U.S. Pat. Nos. 7,679,133; 8,553,466;8,654,587; 8,559,235; and U.S. Pat. Pub. No. 2011/0233648.

It should be understood that example embodiments described herein shouldbe considered in a descriptive sense only and not for purposes oflimitation. Descriptions of features or aspects within each device ormethod according to example embodiments should typically be consideredas available for other similar features or aspects in other devices ormethods according to example embodiments. While some example embodimentshave been particularly shown and described, it will be understood by oneof ordinary skill in the art that variations in form and detail may bemade therein without departing from the spirit and scope of the claims.

What is claimed is:
 1. A vertical memory device, comprising: asubstrate; a plurality of cell blocks on the substrate, each of the cellblocks including, a plurality of channels extending in a first directionvertical to a top surface of the substrate, a plurality of gate linesstacked on top of each other on the substrate, the gate linessurrounding the channels, the gate lines being spaced apart from eachother along the first direction; and a plurality of wirings over thegate lines and electrically connected to the gate lines; and anidentification pattern on the substrate, the identification patterncorresponding to at least one of the plurality of the cell blocks,wherein the identification pattern is at a same level above thesubstrate as a level of at least one of the wirings.
 2. The verticalmemory device of claim 1, wherein the identification pattern is at asame level above the substrate as a level of at least one of thewirings.
 3. The vertical memory device of claim 1, wherein the gatelines extend in a second direction parallel to the top surface of thesubstrate, the plurality of the cell blocks are spaced apart from eachother along a third direction that is parallel to the top surface of thesubstrate, and the third direction crosses the second direction.
 4. Thevertical memory device of claim 1, A vertical memory device, comprising:a substrate; a plurality of cell blocks on the substrate, each of thecell blocks including, a plurality of channels extending in a firstdirection vertical to a top surface of the substrate, a plurality ofgate lines stacked on top of each other on the substrate, the gate linessurrounding the channels, the gate lines being spaced apart from eachother along the first direction; and a plurality of wirings over thegate lines and electrically connected to the gate lines; and anidentification pattern on the substrate, the identification patterncorresponding to at least one of the plurality of the cell blocks,wherein at least one of the cell blocks further includes dummy wiringsadjacent to the wirings.
 5. The vertical memory device of claim 3,further comprising: a cutting pattern on the substrate between the cellblocks.
 6. The vertical memory device of claim 3, further comprising: aplurality of block groups on the substrate and arranged in the thirddirection, wherein each of the block groups include a group of the cellblocks.
 7. The vertical memory device of claim 5, wherein the substrateincludes a cell region and an extension region, the channels are on thecell region, end portions of the gate lines are on the extension region,and the cutting pattern extends over the cell region and the extensionregion.
 8. The vertical memory device of claim 6, further comprising: aplurality of identification patterns on the substrate, wherein theidentification patterns include the identification pattern, theidentification patterns are in each of the block groups.
 9. The verticalmemory device of claim 7, wherein the cutting pattern is a common sourceline.
 10. The vertical memory device of claim 4, wherein a dummy wiringincluded in a cell block of the cell blocks in which the identificationpattern is provided has a different shape from those of remaining dummywirings of the dummy wirings.
 11. A vertical memory device, comprising:a substrate; a plurality of cell blocks on the substrate, each of thecell blocks including, a plurality of channels extending in a firstdirection vertical to a top surface of the substrate, a plurality ofgate lines stacked on top of each other on the substrate, the gate linessurrounding the channels, the gate lines being spaced apart from eachother along the first direction; and a plurality of wirings over thegate lines and electrically connected to the gate lines; and anidentification pattern on the substrate, the identification patterncorresponding to at least one of the plurality of the cell blocks andhaving a shape of a number or a Roman alphabet The vertical memorydevice of claim 1, wherein the identification pattern has a shape of anumber or a Roman alphabet.
 12. A vertical memory device, comprising: asubstrate including a cell region and an extension region; cell blockson the substrate, each of the cell blocks including, channels extendingon the cell region of the substrate in a first direction vertical to atop surface of the substrate, gate lines stacked on top of each other onthe cell region and the extension region of the substrate, the gatelines surrounding the channels, the gate lines being spaced apart fromeach other along the first direction, and end portions of the gate linesbeing on the extension region of the substrate, and wirings over thegate lines and electrically connected to the gate lines; cuttingpatterns extending in a second direction parallel to the top surface ofthe substrate from the cell region to the extension region of thesubstrate, the cutting patterns including a metal, and the metalextending in the first direction to the substrate; and an identificationpattern on the substrate, the identification pattern corresponding to atleast one of the cell blocks, wherein the cell blocks are spaced apartfrom each other by the cutting patterns, the identification pattern isdisposed between neighboring ones of the cutting patterns in a planview, and the identification pattern is at a same level above thesubstrate as a level of at least one of the wirings.
 13. The verticalmemory device of claim 12, wherein the gate lines extend in the seconddirection, the cell blocks are spaced apart from each other along athird direction that is parallel to the top surface of the substrate,and the third direction crosses the second direction.
 14. The verticalmemory device of claim 13, further comprising: a bit line extending inthe third direction on the substrate, the bit line being electricallyconnected to at least one of the channels.
 15. The vertical memorydevice of claim 14, wherein the identification pattern is disposed in anarea defined by the neighboring ones of the cutting patterns extendingin the second direction, the bit line extending in the third direction,and the at least one of the wirings, in a plan view.
 16. The verticalmemory device of claim 14, wherein the identification pattern and thebit line are at the same level.
 17. The vertical memory device of claim12, wherein the identification pattern is at a same level above thesubstrate as a level of a lowermost one of the wirings.
 18. The verticalmemory device of claim 12, further comprising contacts connected to theend portions of the gate lines, respectively, on the extension region ofthe substrate, wherein the wirings are electrically connected to thegate lines via the contacts.
 19. The vertical memory device of claim 12,wherein the gate lines include step portions arranged on the extensionregion of the substrate, and wherein the identification pattern isdisposed between the cell region and the extension region of thesubstrate.
 20. The vertical memory device of claim 12, wherein theidentification pattern has a shape of a number.